Some embodiments described herein relate generally to clock gating. More particularly, some embodiments described herein relate to systems and methods for dynamic coarse clock-gating packet-processing engines for power saving in a device.
Clock gating can be used to deactivate or “turn off” parts of a circuit to reduce the power consumption of a device. A clock signal passes through a logic circuit that can selectively block, or gate, the clock signal. When the clock signal is blocked, logic driven by the gated clock signal suspends operation and does not consume any power. The amount of power savings is related to the amount of logic that is effectively turned off. For example, higher gating on the clock tree (i.e., the clock distribution network) can result in turning off a relatively larger portion of the clock distribution network, thereby using a relatively lower amount of power than would otherwise be used. If the clock is gated at the flip-flop level (for example, immediately before the clock input to a register), very little power is saved because nearly the whole clock network still toggles (e.g., turns on and off).
Some known devices include a two-dimensional array (fabric) or a pool of many relatively small logic elements (referred to herein as packet-processor elements or packet-processing engines (PPEs)). In some instances, a method for clock gating PPEs of a device (such as an application specific integrated circuit (ASIC)) includes monitoring the rate and trend (e.g., increasing or decreasing) of traffic (i.e., workload) experienced at or on an interface. In such instances, the device can include or implement a clock gating method based on the rate and trend of the traffic experienced by the entire device, thereby saving a measure of an amount of power. Because the clock gating is based on the rate of traffic of the entire device, however, in some instances, one or more PPEs can remain powered on even though they are not immediately needed, thereby using power.
Thus, a need exists for improved systems and methods of dynamic coarse clock-gating packet-processing engines for power saving in a device.